The present invention relates to data processing. More particularly, the present invention relates to debugging of a data processing apparatus.
Debugging of a data processing apparatus is a methodical process of finding and reducing the number of bugs or defects in either a computer program running on the data processing apparatus or a piece of electronic hardware comprising the data processing apparatus. As they have developed over time, microprocessors and the software designed to run on them have become more complex so the process of debugging has become progressively more challenging in terms of devising efficient methods and systems to detect defects in operation. It is known to provide a debug mode of a data processing apparatus into which the data processing apparatus is switched in order to execute debug operations.
With the complexity of modern microprocessors, it is now not unusual for a given microprocessor to be capable of executing more than one instruction set. For example the ARM7TDMI® processor core is capable of executing both a regular “A32” instruction set (also known as the “ARM” instruction set) comprising 32-bit wide operation codes, and a more compact instruction set denoted “T32” (also known as the “Thumb” instruction set) that provides a subset of the most commonly used A32 instructions that have been compressed into 16-bit wide operation codes. On execution, the 16-bit wide instructions can be either decompressed to the full 32-bit wide A32 instructions or executed directly using a dedicated decoding unit. Thus a given data processing apparatus can be capable of executing a plurality of different instruction sets. Both the A32 instruction set and the T32 instruction set operate on 32-bit wide data.
In addition to a given data processing apparatus being capable of executing a plurality of different instruction sets, many modern data processing apparatuses are capable of operating in a plurality of different operating states or at a plurality of different “privilege levels”. At different privilege levels, the data processing apparatus imposes on program instructions different access permissions to at least one of memory and a set of registers. For example, the set of control registers accessible to the processing circuitry at a standard privilege level will typically be more restricted than the set of control registers accessible to the data processing apparatus when operating at a higher privilege level, e.g. when a data processing apparatus is operating in a system mode rather than a user mode. When operating at different privilege levels the data processing apparatus will typically apply different virtual to physical memory address translation schemes for translating memory addresses of program instructions.
For example, in data processing systems that implement virtualisation and run a hypervisor to enable a plurality of different guest operating systems to be run on the same data processing apparatus, any privilege level of the data processing apparatus that sits below the privilege level of the hypervisor (i.e. runs under supervision of the hypervisor) will have an additional level of address translation associated with the virtualisation process. The additional level of address translation makes use of a “virtual translation table base register”. However, the privilege level corresponding to the hypervisor layer itself does not require reference to a virtual translation table base register but only to a translation table base register and thus will involve one fewer translation stage.
It is known in processors that are capable of executing a plurality of instruction sets to impose a default debug instruction set for use when the data processing apparatus is in a debug mode. For example, in the ARM10, ARM11 and ARM Cortex processors the default was to use the A32 instruction set whenever the data processing apparatus switched into a debug mode. An alternative known approach used, for example in ARM7TDMI® and ARMS processors is that upon entry to the debug mode the instruction set state remains as it was on entry to the debug mode so that if the data processing apparatus was executing T32 instructions upon entry to the debug mode then T32 instructions would be used for the debug process whereas if the data processing apparatus was executing A32 instructions upon entry to the debug mode then the debug process would be executed using A32 instructions.
However, problems can arise due to the possible mismatch between the operating state of the data processing apparatus i.e. the privilege level at which the data processing apparatus is operating when debug operations are to be performed and the instruction set allocated for use in the debug mode of the data processing apparatus. Thus, for example, the virtual to physical address translation scheme appropriate for the current privilege level of the processor could be incompatible with the chosen debug instruction set. This can present a particular problem in a data processing apparatus configurable to have a variable-width register for instructions because instructions having a larger operand bit-width could have to be used for a debug process whereas the operating state of the processor may mean that a 32-bit virtual to physical address translation scheme should be implemented in the debug mode. This potential mis-match between the processor operating state and the debug instruction set increases the complexity of the debug operations because the debug module hardware will then have to be designed to accommodate a large number of bit patterns corresponding to each of the plurality of instruction sets that can be executed by the data processing apparatus. Thus there is a requirement to reduce the complexity of the debug circuitry yet still offer the flexibility to debug a data processing apparatus capable of operating at a plurality of different privilege levels and/or capable of executing a plurality of different instruction sets.